1. Field of the Invention
This invention relates to a synchronous shift register having series and parallel data inputs and a basic position input and utilizes a number of storage elements which are connected in series. Each of the storage elements is constructed from a master-slave flip-flop and a majority decision circuit for two variables applied to the set and reset inputs and a third variable fed back from the output of the slave is connected with the first input of the master and to its second input by way of an inverter so that the storage element fulfills the truth table
S R Qto Qtl ______________________________________ L O O O L L O L O L L L O O L O L O L L L L L L O L O O O O O O ______________________________________
which corresponds to the Boolean equation EQU Qt1 = S . R + Qto . (S + R).
2. Description of the Prior Art
Shift registers are connected in the form of a chain and can be utilized as parallel-series converters and also vice versa as series-parallel converters. In contrast to the known matrix-type constructed memories in which individual data bits are recorded in the various storage cells where they remain until a change takes place, or until they are recalled, in the case of the shift register constructed as a chain, a data total in the form of a bit pattern is always processed simultaneously. This bit pattern which is contained in the individual storage cells of the shift register is shifted, in general, synchronously into the respective adjacent storage cell by a pulse which is provided in common to all of the storage cells.